1. Field of the Invention
The present invention generally relates to a semiconductor device and a method of forming the same.
Priority is claimed on Japanese Patent Application No. 2009-117951, filed May 14, 2009, the content of which is incorporated herein by reference.
2. Description of the Related Art
Semiconductor integrated circuits have been on the increase in density of integration and on the improvement in performance. As the density of integration of the semiconductor integrated circuit is increased, the area shared by a transistor is reduced and the gate length of the transistor is also reduced. Reduction of the gate length will generally cause short channel effects. In order to prevent the short channel effects, it is difficult to further shrink the semiconductor integrated circuit. In order to solve these issues, a pillar MOS transistor was developed. The pillar MOS transistor includes a semiconductor pillar having a side face on which a gate insulating film is formed. The pillar MOS transistor includes a gate electrode on the gate insulating film. The gate electrode is separated by the gate insulating film from the semiconductor pillar. The pillar MOS transistor includes source and drain which are placed near the top and bottom portions of the semiconductor pillar. The pillar MOS transistor includes a channel which extends along the side face of the semiconductor pillar. The channel length direction is vertical to the surface of a semiconductor substrate. It is possible to increase the channel length without increasing the shared area of the transistor. The pillar structure allows further shrinkage of the semiconductor integrated circuit, while suppressing the short channel effects.